Scalability evaluation of an FPGA-based multi-core architecture with hardware-enforced domain partitioning Kliem, Daniel Voigt, Sven-Ole 2014 - TUHH Open Research
An asynchronous bus bridge for partitioned multi-soc architectures on FPGAs Kliem, Daniel Voigt, Sven-Ole 2013 - TUHH Open Research
Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs Baesler, Malte Voigt, Sven-Ole 2013 - TUHH Open Research - frei zugänglich
A multi-core FPGA-based SoC architecture with domain segregation Kliem, Daniel Voigt, Sven-Ole 2012 - TUHH Open Research
FPGA implementations of radix-10 digit recurrence fixed-point and floating-point dividers Baesler, Malte Voigt, Sven-Ole Teufel, Thomas 2011 - TUHH Open Research
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing Voigt, Sven-Ole Baesler, Malte Teufel, Thomas 2010 - TUHH Open Research
A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGA Baesler, Malte Voigt, Sven-Ole Teufel, Thomas 2010 - TUHH Open Research - frei zugänglich
A radix-10 digit recurrence division unit with a constant digit selection function Baesler, Malte Voigt, Sven-Ole Teufel, Thomas 2010 - TUHH Open Research
An IEEE 754-2008 decimal parallel and pipelined FPGA floating-point multiplier Baesler, Malte Voigt, Sven-Ole Teufel, Thomas 2010 - TUHH Open Research
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on Multi-FPGA platforms Voigt, Sven-Ole 2008 - TUHH Open Research
Analysis of a dynamically reconfigurable dataflow architecture and its scalable paralle extension for multi-FPGA platforms Voigt, Sven-Ole Teufel, Thomas 2008 - TUHH Open Research
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms Voigt, Sven-Ole Teufel, Thomas 2007 - TUHH Open Research
