7 Einträge gefunden

1. FPGA implementations of radix-10 digit recurrence fixed-point and floating-point dividers

   1. Baesler, Malte
   2. Voigt, Sven-Ole
   3. Teufel, Thomas

   2011 - TUHH Open Research
2. An IEEE 754-2008 decimal parallel and pipelined FPGA floating-point multiplier

   1. Baesler, Malte
   2. Voigt, Sven-Ole
   3. Teufel, Thomas

   2010 - TUHH Open Research
3. A radix-10 digit recurrence division unit with a constant digit selection function

   1. Baesler, Malte
   2. Voigt, Sven-Ole
   3. Teufel, Thomas

   2010 - TUHH Open Research
4. Dynamically reconfigurable dataflow architecture for high-performance digital signal processing

   1. Voigt, Sven-Ole
   2. Baesler, Malte
   3. Teufel, Thomas

   2010 - TUHH Open Research
5. A decimal floating-point accurate scalar product unit with a parallel fixed-point multiplier on a Virtex-5 FPGA

   1. Baesler, Malte
   2. Voigt, Sven-Ole
   3. Teufel, Thomas

   2010 - TUHH Open Research - frei zugänglich
6. Analysis of a dynamically reconfigurable dataflow architecture and its scalable paralle extension for multi-FPGA platforms

   1. Voigt, Sven-Ole
   2. Teufel, Thomas

   2008 - TUHH Open Research
7. Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms

   1. Voigt, Sven-Ole
   2. Teufel, Thomas

   2007 - TUHH Open Research